How to Read and Do Proofs : an Introduction to Mathematical Thought Processes 5th Pdf

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Location: Southampton, United kingdom

Nationality: German
Mobile: +44 77 20 400 173
Electronic mail: thomas(at)troeger.com
Web: www.troeger.com

Availability: immediately

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Digital IC Design Engineer

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PROFESSIONAL SUMMARY

German Passport holder, educated to Dipl.Ing. level in Microsystem electronics (equivalent to Masters level), living in the UK for 10 years. Lived and worked in the United states of america, Netherlands, Germany and Hong Kong. Fluent in English, High german and Slovak. I travel worldwide very often and enjoy learning about new cultures. As with my work I have a disciplined and organised arroyo to life exterior it. A flexible and creative personality with strong skills in communication, strategic thinking, co-ordination, problem-solving and time management.

Principle Digital IC Design Engineer with fifteen years feel in taking designs from specification to realisation. The past 9 years accept predominantly been in the field of Digital High Definition Tv, with upward to 26 million gates in 45nm technology. My competence and versatility is such that I was kept past NXP for 9 years despite frequent reductions of internal resources.

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SKILLS & LANGUAGES

Verilog and VHDL coding
Unix scripting
Simulation (Cadency NC-Sim, Mentor Graphics ModelSim)
Verification (Spyglass, code coverage, lint checking)
Synthesis (Synopsys DC)
Xilinx FPGA (ISE)

Actel FPGA (Designer)
DFT (BIST, scan insertion, boundary scan insertion)
SDF dorsum annotated sims (set-up, run)
Static Timing Assay (set-up, run)

Equivalency checking / Formal Verification (Mentor FormalPro, Synopsys Formality, Cadence Verisity)

IC Organization Integration
IC Silicon bring-up and Validation
Project surround definition and set up-up
Database Configuration Management (CVS / Synchronisity TempoSync / ProjectSync)

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Professional HISTORY

EADS Astrium - June 2009 to Present
Migration of FPGA based Satellite-Radar implementation into an ASIC. Tasks involved VHDL modification around Memories and FIFOs, Simulation against FPGA reference design, Synthesis, Purlieus Scan, Scan insertion, Formal Verification. Work with Atmel's Space approved cell library.
Tasks:

• Blueprint modification (VHDL) to supersede Xilinx FPGA memories and Fifos with Atmel'south ASIC equivalent modules
• Implementation of PAD level and Boundary Scan
  
• System verification setup and run (ModelSim)
  
• Full System Synthesis (Synopsys) with Scan insertion
• Hardening of selected cells for Infinite requirements
  
• Formal Verification (FormalPro)
  

Imagination Technologies - Oct 2008 to June 2009 (8 month)
Work on a Loftier Definition Frame Charge per unit Converter, suitable for low-power Mobile Phone requirements. Full VHDL implementation from scratch of two large sub-modules.
Tasks:

• Design implementation (VHDL) of a video cadency detector module and a motion vector controller
• Testbench implementation
  
• Verification / Simulation against C++ models (NC-Sim)
  
• Synthesis (Synopsys)
• Formal Verification (Spyglass)
  

NXP Semiconductors (formerly part of Philips) - September 1999 to July 2008 (9 Years)

Digital IC Blueprint Contractor with leading integration role in Hard disk drive high-end and mainstream digital TV systems. Piece of work on 10 unlike projects of which eight made information technology into mass-market Idiot box production for customers like Philips, Sony, Sharp and Samsung. Six of the projects were completed within 4 weeks of the original fourth dimension scales.

PNX85500 (TV550) - November 2007 - July 2008 (ix month)
Highly integrated TV reception and media processing solutions for the mainstream LCD Tv set market with picture and motion improvement. 26 one thousand thousand gates in CMOS 45nm engineering science.
Tasks:

• Project environment definition and ready-upward with root access for the whole NXP site.
• Close piece of work with IC architects to define, generate and modify Verilog IC infrastructure IPs like register access network, omnibus interfaces, accost converters, interrupt controllers and mucilage logic to see project requirements.

• IC core connectivity, which involves total agreement of the IC architecture specification.
• Close work with NXP internal module suppliers in America, Europe and Asia in guild to guarantee quality and functionality of IPs on time.
• Shut work with back-end team to ensure shine handover of intermediate and final netlist delivery, responding to feedback
  
• Ensure correct DFT implementation and delivery of scan-inserted netlist to test team for pattern generation, responding to feedback
  
• Part of a top level verification team which involves simulation / debugging (Cadence NC) with the use of a self testing surroundings until system employ cases pass as specified.

• Database Configuration Management to continue quality and quantity of ca. i million files used past over 250 users world broad. Ensure compilation of mixed VHDL/Verilog top-level RTL and produce DB releases for verification team and ensure simulation functionality to organisation boot-up.

PNX8543 (TV543) - January 2007 (nine calendar month)
Integrated MPEG-4/H.264 decoder, the TV543 unmarried chip LCD Telly solution.
Tasks: IC core integration, work on infrastructure IPs, simulation (RTL, Netlist, SDF)

PNX5100 - January 2006 (12 month)
Advanced video picture comeback IC, NXP™s Motion Authentic Picture Processing (MAPP), to combine movie judder cancellation, motion sharpness and vivid color management.
Tasks: IC cadre integration, piece of work on infrastructure IPs, simulation (RTL, Netlist, SDF)

PNX8336 (STB236) - September 2005 (4 month)
Ready-Top Box IC with integrated HDMI and 1080p output.
Tasks: Database Configuration Manager to solve a DB quality issues. My experience with like IPs used in Television applications and a similar project surround immune me to ensure that the RTL simulation team, synthesis squad and pinnacle-level netlist integration team are working aligned on ca. 36 IPs.

PNX853x (TV520) - August 2004 (fourteen month)
Highly integrated Television receiver reception and media processing solutions for the mainstream LCD TV market.
Tasks: IC core integration, work on infrastructure IPs, simulation (RTL, Netlist, SDF)

PNX2015 (TV810) - October 2003 (10 calendar month)
Companion IC to provide a 2d HD channel for the US market.
Tasks: Pad level generation, IC core integration, Formal Verification, Acme Level Netlist Integration with Synopsys DC.

PNX8526 (Viper 1.one) - Oct 2002 (12 month)
Highly integrated media processor for use in Advanced Set Top Boxes (ASTB) and Digital Tv (DTV) systems. Decoding 'all format' HD and SD MPEG-2.
Tasks: Total IC validation, bring-up, problem solving and full validation of use cases, close work with external customers in solving issues while bringing devices to TV mass production

ADOC - December 2000 (20 month)
Analog TV IC with digital audio / video processing. This multi-site project was several times larger than previous projects with a large learning curve.
Tasks: piece of work on internal control core, integration of external audio and video cores, simulation

Painter Leader (UOC) - April 2000 (eight calendar month)
"Ultimate One Chip", low-cease analogue Idiot box awarding with teletext for the mass-market
Tasks: IC Validation of teletext

VMIPS - September 1999 (7 month)
Tasks: Testbench implementation

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Pace to self employment in Jan 2000 with move to Britain after v years employment with Sican GmbH  (now Silicon Epitome) in Hannover, Frg

Texas Instruments in Dallas, Texas - March 1999 to September 1999 (7 months)
Implementation / Verification Engineer for DSP/ASP Grouping
Sole responsibility in defining & implementing exam cases for a Flashmemory Controller Evolution. The testbench was written from scratch using my strong VHDL blueprint knowledge I have learned during my time at Alcatel. After setting upwards a command based and cocky testing testbench information technology was easy and quick to write new tests to cover test cases.

Alcatel in Stuttgart- February 1998 – March 1999 (1 year 2 months)
Design Engineer - Telecommunication Multiswitch
Specification, implementation and verification of SDH/Sonet modules in VHDL
Gained very good VHDL knowledge from Alcatel's structured design rules. Work with the SDH/Sonet telecommunications protocol was 1 the most challenging projects.

Siemens in Munich - September 1997 – February 1998 (6 months)
Blueprint Engineer - Microcontroller Development
Implementation and verification of a DMA module

ARM in Cambridge - Baronial 1997 – September 1997 (2 months)
Technical Consultant - Telemetry Application
Specification and implementation of LAN and PCI interface adaptor to the ARM - AMBA - Bus

Philips in Nijmegen, Netherlands - April 1997 – Baronial 1997 (5 months)
Pattern Engineer - Mobile Telecommunications Device Realization
Specification, implementation and verification of a depression ability ARM design

Ericsson in Hannover & Stockholm - April 1996 – April 1997 (one year 1 month)
Pattern Engineer
Applied science migration of a Telecommunication ASIC with test structure and RAM insertion
Synthesis, Boundary Browse, Full Scan

Sican GmbH in Hannover - December 1995 – April 1996 (5 months)
Design Engineer

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